Generally, copper wires are extensively employed as interconnections on a chip when applying the damascene process in semiconductor fabrication. As the semiconductor device densities are reduced, there is a desire to reduce the cross sectional area of the copper interconnects and/or its pathway distance. This can typically result in an increased resistance of the copper interconnect, which in turn can require a larger voltage and current to drive a signal. The larger voltage and current can result in a greater risk for capacitive coupling and signal errors during the operation of the integrated circuit. Moreover, the stringent demand placed on interconnects for advanced ultra-large-scale integration (ULSI) technologies, may compel metallization schemes other than copper based designs to achieve high current densities and faster switching speeds.
At the same time, there is a continuous desire to increase the storage capacity of the integrated circuit, as computers are consistently becoming more powerful and new and improved electronic devices are continually developed (e.g., digital audio players, video players). Such growth and development has vastly increased the amount of information required to be stored in the semiconductor chip or the integrated circuit and its memory cells.
A relatively recent type of memory cell is an organic based memory cell. Organic memory cells are at least partly based on organic materials and, are thus able to overcome some of the limitations of inorganic based memory cells. Organic memory cells facilitate increases in device density, while also increasing device performance relative to conventional inorganic memory cells. Additionally, organic memory cells are non-volatile and, as such; do not require frequent refresh cycles or constant power. Such cells can have two or more states corresponding to various levels of impedance. These states are set by applying a bias voltage, and then the cells remain in their respective states until another voltage, in reverse bias, is applied. The cells maintain their states with or without power (e.g., non-volatile) and can be read either electrically or optically by measuring injection current or light emission, for example.
Typically, these multiple layered memory cells can be formed with difficulty, unless the substrate topography is planarized in an early stage of the manufacturing process. Put differently, the substrate topography should be as close to a planar and smooth surface as possible. Problems arise when micro scratches that adversely affect surface smoothness are formed during the chemical mechanical polishing process (CMP) step of the semiconductor fabrication.
In general, fabricating an integrated circuit (IC) includes sequentially depositing conducting, semi conducting and/or insulating layers on a silicon wafer, wherein portions of the conductive metal remaining between the raised patterns of an insulating layer can form vias, plugs and/or lines that are filled with a conducting metal. One step in the fabrication process is the CMP.
Typically, the CMP process involves holding a thin flat wafer against a rotating wetted polishing surface under a controlled downward pressure. A polishing slurry, such as a solution of alumina or silica, may be used as the abrasive medium. A rotating polishing head or wafer carrier is generally employed to hold the wafer under controlled pressure against a rotating polishing platen. The polishing platen is typically covered with a relatively soft wetted pad material such as blown polyurethane.
The mechanics of metal CMP include, for example, chemically forming an oxide of the metal on the metal film surface on the wafer. The oxide is then removed mechanically via, for example, abrasives in the slurry. The mechanics of other CMP (e.g., polysilicon polish, dielectric polish) similarly involve a chemical reaction followed by a mechanical removal of reaction products.
The polishing pad facilitates removing reaction products at the wafer interface to facilitate layer thickness production. For example, CMP processes can be employed to remove around 0.5 to 1.0 μm of material. The polishing pads may vary, for example, in hardness and density. For example, pads can be relatively stiff or relatively flexible. A less stiff pad will conform more easily to the topography of a wafer and thus while reducing planarity may facilitate faster removal of material in down areas. Conversely, a stiffer pad may produce better planarity, but may result in slower removal in down areas.
Some goals of CMP include achieving general planarity across a wafer, creating a desired film thickness uniformity, removing chemical reaction products and/or layers at a desired rate and achieving desired selectivity and/or endpoint. The achievement of these goals partly depend upon, the concentration of solids in the slurry (e.g. the number and size of abrasive particles suspended in the slurry), the chemical composition of the slurry (e.g. the pH of the slurry and/or the presence of acids or bases added to the slurry to facilitate chemical reactions associated with CMP processing), the distribution of the slurry, the degree of contact between one or more polishing pads, polishing pad attributes (e.g. porosity, density, flexibility), the rate at which slurry is fed onto polishing pads and/or the wafer and the size, number and arrangement of grooves machined into the bulk silicon wafer to channel slurry about the entire wafer surface. The degree of wafer-pad contact can, for example, affect the uniformity of slurry as polishing pads rotate and move relative to the wafer, thus, pushing slurry around on the wafer.
The rate at which CMP progresses may also vary depending on parameters of the slurry employed. Slurries may consist, for example, of small abrasive particles suspended in a solution (e.g., aqueous solution). Acids or bases can be added to such solutions to facilitate, for example, the oxidation of the metal on the wafer and/or other chemical reactions involved in other non-metal CMP processes. Slurry parameters that can impact polishing rates include, for example, the chemical composition of the slurry, the concentration of solids in the slurry, the solid particles in the slurry and the temperature of the wafer to which the slurry is applied.
A particular problem encountered in the CMP process is the formation of micro scratches on the polished surface. These micro scratches may be damaging to the inter-connection levels created during the damascene technique, for example because the metal layer that is deposited on the surface will become trapped in the scratch, thus causing short failure of the IC chip. Also, these micro-structure irregularities adversely affect the smoothness and planarity of the substrate layer upon which the organic memory cells are to be subsequently formed. Accordingly, there exists a need in the art to provide a reliable way to remove scratches formed in the substrate layer that form the base of the organic memory cells.
At the same time, the need for higher circuit densities and faster switching speeds generally compels the formation of these organic memory cells on a substrate layer that demonstrates improved conductive electrical properties over the conventional copper substrate. Thus, there also exists a need in the art to form the organic memory cell structures on metallization schemes with improved electrical conductivity.